This invention relates to a mixed signal (e.g., analog level and stochastic temporal pattern) implementation of a belief propagation processor.
Soft logic processing with analog values has a number of applications, including in decoding of Low Density Parity Check (LDPC) codes. A number of algorithms have been proposed for either processing digital or analog representations of values, including the Sum-Product (SP) algorithm, which is sometimes referred to as a Belief Propagation Algorithm, and the Min-Sum (MS) algorithm (also referred to as Max-Sum or Max-Product), which can be regarded as an approximation of the SP algorithm. A description of such algorithms may be found in H. Wymeersch, Iterative Receiver Design, Cambridge University Press, Cambridge, 2007.
Implementations of the Sum-Product (SP) algorithm for error correction decoding generally involve two kinds of soft-gates: Equals and XOR. The connectivity between the Soft equals and Soft XOR is based on the check-matrix associated with the specific error correcting code.
In some implementations of the Sum-Product algorithm, messages are passed between Soft Equals and Soft XOR gates as stochastic signals that randomly vary between a set of signal values (e.g., between a set of two possible values, such as 0 and 1 volt) such that the average of the signal over time represents the message value. An example of such implementation is described in C. Winstead et al., “Stochastic Iterative Decoders,” Cornell Computing Research Repository (CoRR) (2005), http://arxiv.org/abs/cs/0501090. Such stochastic implementations face challenged including correlation of stochastic signals and/or complexity or resource requirements of circuitry for addressing such possible correlation.